This invention relates to a complex semiconductor device, more particularly a semiconductor device incorporated with semiconductor elements having complementary characteristic through a dielectric isolating structure.
Various types of the semiconductor devices of the type just mentioned have been developed for use in various applications. Although, semiconductor devices having satisfactory characteristics for certain applications have been developed, semiconductors having satisfactory characteristics for different applications have not yet been developed. For example, as a result of recent development in the art of electronics, modern telephone exchange equipments are fabricated with electronic elements, and time division type electronic telephone exchange equipments have been developed for the purpose of improving efficiency and satisfying various service requirements. Although such electronic telephone exchange equipments are advantageous in that they can meet various service requirements and can be applied directly to digital transmitting systems without requiring any special processing, their cost of manufacturing is considerably higher than the prior art telephone exchange equipment. The reason for increasing the manufacturing cost lies in that it is necessary to provide a bidirectional talking supply current, a rate pulse, etc. to subscriber lines for respective subscribers. Since such supply circuit supplies to the lines a large current of 120 mA, for example, it is necessary to fabricate, with integrated circuit technique, switching transistors utilized to switch such large current sufficient to withstand high voltage, for example 240 V, and to have excellent complementary characteristics.
The following are some of the prior art transistors suitable for such applications. U.S. Pat. No. 3,818,583 discloses complementary transistors in which an N.sup.- island and a P island are isolated by a dielectric by unique combination of a selective diffusion of a P.sup.+ impurity into an N.sup.- substrate, a passivation of islands with oxidized film and a vapor deposition of thick polycrystalline silicon film.
With this construction, it is easy to form an N type transistor having a breakdown strength of about several hundreds volts in the N.sup.- island, since the impurity concentration in the N.sup.- island is made to be 5.times.10.sup.14 /cm.sup.3, for example. However, it is impossible to obtain a P type transistor having a high breakdown strength, because the P island is formed by heat diffusion of a P type impurity into the N.sup.- substrate, thus failing to sufficiently decrease the impurity concentration. Moreover, with this construction, high impurity concentration layer can be formed only on the bottom surface of the N.sup.- island with the result that a relatively large series resistance is added to the transistor formed in the N.sup.- island, thus narrowing the dynamic operating range of the transistor. Furthermore, heat treatment at a high temperature over a long time is necessary to form the P island by heat diffusion of a P type impurity into the N.sup.- substrate which is of course undesirable from the standpoint of manufacturing cost.
Furthermore, U.S. Pat. No. 3,461,003 discloses a construction in which the N.sup.- island and the P.sup.- island are selectively formed by epitaxial growth technique and in which respective islands are surrounded by a dielectric and supported by polycrystalline silicon. With this construction, since respective islands are formed with epitaxial growth technique, it is not only possible to control the impurity concentration in respective islands to any desired value but also possible to make high the impurity concentration of the portions of the islands contiguous to the dielectric, thereby attaining complementary transistors having a high breakdown strength and a low resistance. With this construction, however, as respective islands are formed by selective epitaxial growth technique, the cross-sectional configuration of respective islands becomes rectangular of an inverted frustum, thus making it difficult to control its shape, or the formation of the vertical walls. The polycrstalline layers between respective islands would not be formed in the vapor deposition process sufficiently near the side walls, particularly near the bases of these islands since they have vertical or overhung walls, thus forming cavities of recesses which cause the fracture of the wafer.
Furthermore, in this construction, the range of conditions of the selective epitaxial growth is narrow, thus makes it difficult to control processes. With this construction, it is extremely difficult to form thick islands having a thickness of several tens microns.
During the photoetching step for forming a P island subsequent to the formation of an N island, it is difficult to correctly control photoetching due to the presence of a large shoulder caused by the N island.